The present invention relates generally to a method, system, and computer program product for electronic design automation, and more particularly to a method, system, and computer program product for slack stealing improvement.
Electronic design automation (EDA) is used to design integrated circuits. Integrated circuit or chip designers use EDA for analysis and design optimization of a semiconductor chip design. Analysis of the semiconductor chip design includes timing analysis, which can provide measurements of slack times of transparent latches in the semiconductor chip design. Design slack improvement can be performed by slack stealing, cycle stealing, or cycle steal adjusts, which will move available slack from either an input or output side of a latch or electrical component to another output or input of the component, by design adjustments to modify a clock launch and/or a data line arrival time.
Slack time can be defined as an amount of time a task can be delayed without causing another task to be delayed or impacting the completion time of an electrical circuit design. Slack time, or slack, is a difference between a desired time or required time for a timing path and an achieved time or arrival time for the timing path. When an input to a latch arrives later than desired, this results in a negative input slack, or the desired time is before the achieved time. A negative slack means that a data signal is unable to traverse Boolean or combinational logic between a start point and an endpoint of a timing path fast enough to ensure an electrical circuit functions as designed. Alternatively, when an input to the latch arrives sooner than desired, this results in a positive input slack, or the achieved time is before the desired time. An arrival time is the latest or earliest time at which an electrical signal output from the latch may switch at a given location within the design. When an input or output on a latch is available later than desired, this results in a negative input/output slack, and when the input/output on the latch is available sooner than desired, this results in a positive input/output slack.